Information about cable, connector or adapter : PCI Express 8x  

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 PCI Express 8x
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 Copyright :
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 Category :   All cables and connectors > Connectors > Computer > Buses >
 Added to database : 2005-12-15 13:47:09



 Description : PCI Express was introduced to overcome the limitations of the original PCI bus. Developed and released by Intel over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology � bus bandwidth is shared among multiple devices - to enable communication among the different devices on the bus.
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PCI Express 8x

 PCI Express 1x - 98 pin Female Connector

 Pinout : 0


PinNameDirectionColorDescription
1B+12v+12 volt power
2+12v+12 volt power
3RSVDReserved
4GNDGround
5SMCLKSMBus clock
6SMDATSMBus data
7GNDGround
8+3.3v+3.3 volt power
9JTAG1+TRST#
103.3Vaux3.3v volt power
11WAKE#Link Reactivation
12RSVDReserved
13GNDGround
14HSOp(0)Transmitter Lane 0, Differential pair
15HSOn(0)
16GNDGround
17PRSNT#2Hotplug detect
18GNDGround
19HSOp(1)Transmitter Lane 1, Differential pair
20HSOn(1)
21GNDGround
22GNDGround
23HSOp(2)Transmitter Lane 2, Differential pair
24HSOn(2)
25GNDGround
26GNDGround
27HSOp(3)Transmitter Lane 3, Differential pair
28HSOn(0)
29GNDGround
30RSVDReserved
31PRSNT#2Hot plug detect
32GNDGround
33HSOp(4)Transmitter Lane 4, Differential pair
34HSOn(4)
35GNDGround
36GNDGround
37HSOp(5)Transmitter Lane 5, Differential pair
38HSOn(5)
39GNDGround
40GNDGround
41HSOp(6)Transmitter Lane 6, Differential pair
42HSOn(6)
43GNDGround
44GNDGround
45HSOp(7)Transmitter Lane 7, Differential pair
46HSOn(7)
47GNDGround
48PRSNT#2Hot plug detect
49GNDGround
1APRSNT#1Hot plug presence detect
2+12v+12 volt power
3+12v+12 volt power
4GNDGround
5JTAG2TCK
6JTAG3TDI
7JTAG4TDO
8JTAG5TMS
9+3.3v+3.3 volt power
10+3.3v+3.3 volt power
11PWRGDPower Good
12GNDGround
13REFCLK+Reference Clock Differential pair
14REFCLK-
15GNDGround
16HSIp(0)Receiver Lane 0, Differential pair
17HSIn(0)
18GNDGround
19RSVDReserved
20GNDGround
21HSIp(1)Receiver Lane 1, Differential pair
22HSIn(1)
23GNDGround
24GNDGround
25HSIp(2)Receiver Lane 2, Differential pair
26HSIn(2)
27GNDGround
28GNDGround
29HSIp(3)Receiver Lane 3, Differential pair
30HSIn(3)
31GNDGround
32RSVDReserved
33RSVDReserved
34GNDGround
35HSIp(4)Receiver Lane 4, Differential pair
36HSIn(4)
37GNDGround
38GNDGround
39HSIp(5)Receiver Lane 5, Differential pair
40HSIn(5)
41GNDGround
42GNDGround
43HSIp(6)Receiver Lane 6, Differential pair
44HSIn(6)
45GNDGround
46GNDGround
47HSIp(7)Receiver Lane 7, Differential pair
48HSIn(7)
49GNDGround

 Note : PCI
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