| Pinout for:PCI Express 8x |
Description : PCI Express was introduced to overcome the limitations of the original PCI bus. Developed and released by Intel over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology � bus bandwidth is shared among multiple devices - to enable communication among the different devices on the bus.
PCI Express 1x - 98 pin Female Connector
Pinout :
| Pin | Name | Description |
| 1B | +12v | +12 volt power |
| 2 | +12v | +12 volt power |
| 3 | RSVD | Reserved |
| 4 | GND | Ground |
| 5 | SMCLK | SMBus clock |
| 6 | SMDAT | SMBus data |
| 7 | GND | Ground |
| 8 | +3.3v | +3.3 volt power |
| 9 | JTAG1 | +TRST# |
| 10 | 3.3Vaux | 3.3v volt power |
| 11 | WAKE# | Link Reactivation |
| 12 | RSVD | Reserved |
| 13 | GND | Ground |
| 14 | HSOp(0) | Transmitter Lane 0, Differential pair |
| 15 | HSOn(0) | |
| 16 | GND | Ground |
| 17 | PRSNT#2 | Hotplug detect |
| 18 | GND | Ground |
| 19 | HSOp(1) | Transmitter Lane 1, Differential pair |
| 20 | HSOn(1) | |
| 21 | GND | Ground |
| 22 | GND | Ground |
| 23 | HSOp(2) | Transmitter Lane 2, Differential pair |
| 24 | HSOn(2) | |
| 25 | GND | Ground |
| 26 | GND | Ground |
| 27 | HSOp(3) | Transmitter Lane 3, Differential pair |
| 28 | HSOn(0) | |
| 29 | GND | Ground |
| 30 | RSVD | Reserved |
| 31 | PRSNT#2 | Hot plug detect |
| 32 | GND | Ground |
| 33 | HSOp(4) | Transmitter Lane 4, Differential pair |
| 34 | HSOn(4) | |
| 35 | GND | Ground |
| 36 | GND | Ground |
| 37 | HSOp(5) | Transmitter Lane 5, Differential pair |
| 38 | HSOn(5) | |
| 39 | GND | Ground |
| 40 | GND | Ground |
| 41 | HSOp(6) | Transmitter Lane 6, Differential pair |
| 42 | HSOn(6) | |
| 43 | GND | Ground |
| 44 | GND | Ground |
| 45 | HSOp(7) | Transmitter Lane 7, Differential pair |
| 46 | HSOn(7) | |
| 47 | GND | Ground |
| 48 | PRSNT#2 | Hot plug detect |
| 49 | GND | Ground |
| 1A | PRSNT#1 | Hot plug presence detect |
| 2 | +12v | +12 volt power |
| 3 | +12v | +12 volt power |
| 4 | GND | Ground |
| 5 | JTAG2 | TCK |
| 6 | JTAG3 | TDI |
| 7 | JTAG4 | TDO |
| 8 | JTAG5 | TMS |
| 9 | +3.3v | +3.3 volt power |
| 10 | +3.3v | +3.3 volt power |
| 11 | PWRGD | Power Good |
| 12 | GND | Ground |
| 13 | REFCLK+ | Reference Clock Differential pair |
| 14 | REFCLK- | |
| 15 | GND | Ground |
| 16 | HSIp(0) | Receiver Lane 0, Differential pair |
| 17 | HSIn(0) | |
| 18 | GND | Ground |
| 19 | RSVD | Reserved |
| 20 | GND | Ground |
| 21 | HSIp(1) | Receiver Lane 1, Differential pair |
| 22 | HSIn(1) | |
| 23 | GND | Ground |
| 24 | GND | Ground |
| 25 | HSIp(2) | Receiver Lane 2, Differential pair |
| 26 | HSIn(2) | |
| 27 | GND | Ground |
| 28 | GND | Ground |
| 29 | HSIp(3) | Receiver Lane 3, Differential pair |
| 30 | HSIn(3) | |
| 31 | GND | Ground |
| 32 | RSVD | Reserved |
| 33 | RSVD | Reserved |
| 34 | GND | Ground |
| 35 | HSIp(4) | Receiver Lane 4, Differential pair |
| 36 | HSIn(4) | |
| 37 | GND | Ground |
| 38 | GND | Ground |
| 39 | HSIp(5) | Receiver Lane 5, Differential pair |
| 40 | HSIn(5) | |
| 41 | GND | Ground |
| 42 | GND | Ground |
| 43 | HSIp(6) | Receiver Lane 6, Differential pair |
| 44 | HSIn(6) | |
| 45 | GND | Ground |
| 46 | GND | Ground |
| 47 | HSIp(7) | Receiver Lane 7, Differential pair |
| 48 | HSIn(7) | |
| 49 | GND | Ground |
Note : PCI